1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more specifically, to a semiconductor integrated circuit device in which a substrate bias is controlled.
2. Description of the Related Art
A semiconductor integrated circuit device using a MOSFET, in order to reduce a power consumption in a standby state, a technique which applies a deep substrate bias to an element to increase a threshold voltage and to reduce a leakage current is popularly used. However, depending on characteristics of elements, when a substrate bias has a depth which is equal to or larger than a predetermined value, a phenomenon to increase a leakage current on the contrary is caused by an effect such as GIDL (Gate Induced Drain Leakage). Therefore, in order to reduce a leakage current as much as possible, the substrate bias must be controlled to a predetermined value. The GIDL is the following phenomenon, that is, when a negative bias and a positive bias are applied to a gate electrode and a drain electrode, respective, a depletion layer extends into a drain region, and an electric field density increases in the region in which the depletion layer extends. For this reason, electrons cause BTBT (Band To Band Tunneling) to cause a leakage current to flow.
In order to calculate an optimum substrate bias value at which a leakage current is minimized, for example, in LOW POWER ELECTRONICS AND DESIGN, 2003. ISLPED '03. PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON, 25-27 Aug. 2003, p. 116-121, by using a circuit shown in FIG. 1, a substrate leakage current serving as a main component of the leakage current is compared with a subthreshold leakage current. In this conventional technique, by using characteristics in which the substrate leakage current increases and the subthreshold leakage current decreases as the substrate bias is made deep, a value at which the substrate leakage current is equal to the subthreshold leakage current is set as a substrate bias value.
For example, in JP-2004-165649A, a substrate bias dependence of a leakage current is previously measured to directly calculate a substrate bias value at which the leakage current is minimized.
However, in the circuit shown in FIG. 1, it is assumed that a subthreshold leakage current obtained by vertically stacked elements can be neglected. This assumption is based on the premise that a DIBL (Drain Induced Barrier Lowering) effect and a substrate effect are great. For this reason, when the DIBL effect and the substrate effect are small, a detection error of the leakage current increases. Furthermore, since a gate leakage current is neglected as a small current, when the gate leakage current is large, the detection error increases. For example, in an element having characteristics shown in FIG. 2, since an inter-gate-substrate current is large, a bias at which a total leakage current is minimum is approximately −1 V. When the circuit shown in FIG. 1 is applied to the element, the substrate bias at which the leakage current is minimum is determined as −2 V in comparison between the subthreshold leakage current and the inter-drain-substrate current, and an actual leakage current is several times the leakage current obtained when the substrate bias is −1 V. In addition, in the conventional technique in FIG. 1, a plurality of leakage currents are detected in different elements, respectively. For this reason, the detection error increases because of fluctuations in characteristic and temperature of the elements.
Furthermore, the substrate bias dependence of a leakage current must be measured in advance by the method described in JP-2004-165649A. For this reason, when the characteristics of an element vary due to a change in temperature or the like, the measurement of the substrate bias dependence must be performed each time the characteristics of the element vary. If a value at which the leakage current is minimum is automatically measured in a chip, a mechanism which holds a current value and a potential value is required.